ATMEGA329P-20MN Atmel, ATMEGA329P-20MN Datasheet - Page 35

• Manufacturer Part Number: ATMEGA329P-20MN
• Description: IC MCU AVR 32K 20MHZ 64QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329P-20MN

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.11
8.11.1
8.11.2
8021G–AVR–03/11
Register Description
OSCCAL – Oscillator Calibration Register
CLKPR – Clock Prescale Register
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. A pre-programmed calibration value is
automatically written to this register during chip reset, giving the Factory calibrated frequency as
specified in
the oscillator frequency. The oscillator can be calibrated to frequencies as specified in
4 on page
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more
than 8.8MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
The CAL6...0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the
range.
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3:0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-
nous peripherals is reduced when a division factor is used. The division factors are given in
Table 8-13 on page
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
Bit
(0x66)
Read/Write
Initial Value
Bit
(0x61)
Read/Write
Initial Value
335. Calibration outside that range is not guaranteed.
Table 28-4 on page
CLKPCE
CAL7
R/W
R/W
7
7
0
36.
CAL6
R/W
6
R
6
–
0
335. The application software can write this register to change
CAL5
R/W
5
R
5
–
0
Device Specific Calibration Value
CAL4
R/W
4
R
4
–
0
CLKPS3
CAL3
R/W
R/W
3
3
ATmega329P/3290P
CLKPS2
See Bit Description
CAL2
R/W
R/W
2
2
CLKPS1
CAL1
R/W
R/W
1
1
CLKPS0
CAL0
R/W
R/W
0
0
Table 28-
OSCCAL
CLKPR
35