ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 103
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 103 of 309
- Download datasheet (6Mb)
7799D–AVR–11/10
Table 15-4
rect PWM mode.
Table 15-4.
Note:
• Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode
These bits control the Output Compare pin (OC0B) behavior. If one or both of the COM0B[1:0]
bits are set, the OC0B output overrides the normal port functionality of the I/O pin it is connected
to. However, note that the Data Direction Register (DDR) bit corresponding to the OC0B pin
must be set in order to enable the output driver.
When OC0B is connected to the pin, the function of the COM0B[1:0] bits depends on the
WGM0[2:0] bit setting.
bits are set to a normal or CTC mode (non-PWM).
[
Table 15-5.
Table 15-3
PWM mode.
Table 15-6.
Note:
COM0A1
COM0B1
COM0B1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
shows the COM0A1:0 bit functionality when the WGM0[2:0] bits are set to phase cor-
pare Match is ignored, but the set or clear is done at TOP. See
page 99
pare Match is ignored, but the set or clear is done at TOP. See
for more details.
shows the COM0B[1:0] bit functionality when the WGM0[2:0] bits are set to fast
Compare Output Mode, Phase Correct PWM Mode
Compare Output Mode, non-PWM Mode
Compare Output Mode, Fast PWM Mode
COM0A0
COM0B0
COM0B0
for more details.
0
1
0
1
0
1
0
1
0
1
0
1
Table 15-2
Description
Normal port operation, OC0A disconnected.
WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.
Clear OC0A on Compare Match when up-counting. Set OC0A on
Compare Match when down-counting.
Set OC0A on Compare Match when up-counting. Clear OC0A on
Compare Match when down-counting.
Description
Normal port operation, OC0B disconnected.
Toggle OC0B on Compare Match
Clear OC0B on Compare Match
Set OC0B on Compare Match
Description
Normal port operation, OC0B disconnected.
Reserved
Clear OC0B on Compare Match, set OC0B at TOP
Set OC0B on Compare Match, clear OC0B at TOP
shows the COM0A[1:0] bit functionality when the WGM0[2:0]
ATmega8U2/16U2/32U2
(1)
(1)
“Phase Correct PWM Mode” on
“Fast PWM Mode” on page 97
103
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