ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 76
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
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- Download datasheet (6Mb)
7799D–AVR–11/10
.Table 12-4
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT..
Table 12-4.
Table 12-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 12-5 on page
PB7/OC0A/OC1C/
PCINT7
0
0
0
0
OC0A/OC1C ENABLE
OC0A/OC1C
PCINT7 • PCIE0
1
PCINT7 INPUT
–
PB3/MISO/PCINT3/
PDO
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE OUTPUT
PCINT3 • PCIE0
1
SPI MSTR INPUT
PCINT3 INPUT
–
and
Overriding Signals for Alternate Functions in PB7..PB4
Overriding Signals for Alternate Functions in PB3..PB0
Table 12-5
relate the alternate functions of Port B to the overriding signals
72. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB2/MOSI/PCINT2/
PDI
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR OUTPUT
PCINT2 • PCIE0
1
SPI SLAVE INPUT
PCINT2 INPUT
–
PCINT6 • PCIE0
PB6/PCINT6
0
0
0
0
0
0
1
PCINT6 INPUT
–
ATmega8U2/16U2/32U2
PB5/PCINT5
0
0
0
0
0
0
PCINT5 • PCIE0
1
PCINT5 INPUT
–
PB1/SCK/
PCINT1
SPE • MSTR
PORTB1 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
PCINT1 • PCIE0
1
SCK INPUT
PCINT1 INPUT
–
PB4/T1/PCINT4
0
0
0
0
0
0
PCINT4 • PCIE0
1
PCINT4 INPUT
T1 INPUT
–
PB0/SS/PCINT0
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
0
0
PCINT0 • PCIE0
1
SPI SS
PCINT0 INPUT
–
76
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