ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 87
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 87 of 309
- Download datasheet (6Mb)
13.2.7
13.2.8
7799D–AVR–11/10
PCMSK0 – Pin Change Mask Register 0
PCMSK1 – Pin Change Mask Register 1
• Bit 1:0 – PCIF[1:0]: Pin Change Interrupt Flag 1:0
When a logic change on any PCINT[12:8]/[7:0] pin triggers an interrupt request, PCIF1/0
becomes set (one). If the I-bit in SREG and the PCIE1/0 bit in EIMSK are set (one), the MCU will
jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 7:0 – PCINT[7:0]: Pin Change Enable Mask 7:0
Each PCINT[7:0] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[7:0] is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT[7:0] is cleared, pin change interrupt on the corresponding I/O
pin is disabled.
• Bit 4:0 – PCINT[12:8]: Pin Change Enable Mask 12:8
Each PCINT[12:8] bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT[12:8] is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT[12:8] is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
Bit
(0x6B)
Read/Write
Initial Value
Bit
(0x6C)
Read/Write
Initial Value
PCINT7
R/W
R
7
0
7
0
-
PCINT6
R/W
R
6
0
6
0
-
PCINT5
R/W
R/W
5
0
5
0
-
PCINT12
PCINT4
R/W
R/W
4
0
4
0
PCINT11
PCINT3
ATmega8U2/16U2/32U2
R/W
R/W
3
0
3
0
PCINT10
PCINT2
R/W
R/W
2
0
2
0
PCINT1
PCINT9
R/W
R/W
1
0
1
0
PCINT8
PCINT0
R/W
R/W
0
0
0
0
PCMSK0
PCMSK1
87
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