ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 211
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ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 211 of 309
- Download datasheet (6Mb)
21.18.3
7799D–AVR–11/10
UDIEN – USB Device Interrupt Enable Register
• Bit 4 – WAKEUPI: Wake-up CPU Interrupt Flag
This flag is set by hardware when the USB controller detects a non-idle signal from the USB
lines. This WAKEUPI flag can generate a “USB general interrupt” if WAKEUPE bit is set. Writing
this bit to zero acknowledges the interrupt source. Writing this bit to one has no effect.Shall be
cleared by software. Setting by software has no effect.
See
• Bit 3 – EORSTI: End Of Reset Interrupt Flag
This flag is set by hardware when the USB controller detects an “End Of Reset” event on the
USB lines. has been detected by the USB controller. This EORSTI flag can generate a “USB
general interrupt” if EORSTE bit is set. Writing this bit to zero acknowledges the interrupt source
(USB clocks must be enabled before). Writing this bit to one has no effect.
Shall be cleared by software. Setting by software has no effect.
• Bit 2 – SOFI: Start Of Frame Interrupt Flag
This flag is set by hardware when the USB controller detects a Start Of Frame PID (SOF) on the
USB lines. This SOFI flag can generate a “USB general interrupt” if SOFE bit is set. Writing this
bit to zero acknowledges the interrupt source (USB clocks must be enabled before). Writing this
bit to one has no effect.
• Bit 1 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 0 – SUSPI: Suspend Interrupt Flag
This flag is set by hardware when the USB controller detects a suspend state on the bus (idle
state for more than 3ms). This SUSPI flag can generate a USB general interrupt if SUSPE bit is
set. Writing this bit to zero acknowledges the interrupt source (USB clocks must be enabled
before). Writing this bit to one has no effect.
See
The interrupt flag bits are set even if their corresponding ‘Enable’ bits is not set.
• Bit 7 – Res: Reserved
This bit is reserved and will always read as zero.
• Bit 6 – UPRSME: Upstream Resume Interrupt Enable Bit
Writing this bit to one enables interrupt on UPRSMI flag. An Upstream resume interrupt will be
generated only if the UPRSME bit is set to one, the Global Interrupt Flag in SREG is written to
one and the UPRSMI bit is set.
Bit
(0xE2)
Read/Write
Initial Value
“Suspend, Wake-up and Resume” on page 200
“Suspend, Wake-up and Resume” on page 200
R
7
0
-
UPRSME
R/W
6
0
EORSME
R/W
5
0
WAKEUPE
R/W
4
0
EORSTE
ATmega8U2/16U2/32U2
R/W
for more details.
for more details.
3
0
SOFE
R/W
2
0
R
1
0
-
SUSPE
R/W
0
0
UDIEN
211
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