ATMEGA32U2-MU Atmel, ATMEGA32U2-MU Datasheet - Page 78
ATMEGA32U2-MU
Manufacturer Part Number
ATMEGA32U2-MU
Description
MCU AVR USB 32K FLASH IND 32VQFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32U2-MU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
Processor Series
ATMEGA32x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
2.5 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK524 - KIT STARTER ATMEGA32M1/MEGA32C1ATSTK600 - DEV KIT FOR AVR/AVR32ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
- Current page: 78 of 309
- Download datasheet (6Mb)
7799D–AVR–11/10
Reset, Reset input. External Reset input is active low and enabled by unprogramming ("1") the
RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when the
pin is used as the RESET pin.
dW, debugWire channel. When the debugWIRE Enable (DWEN) Fuse is programmed and Lock
bits are unprogrammed, the debugWIRE system within the target device is activated. The
RESET port pin is configured as a wired -AND (open-drain) bi-directional I/O pin with pull-up
enabled and becomes the communication gateway between the target and the emulator.
• XTAL2, Bit 0
XTAL2, Oscillator. The PC0 pin can serve as Inverting Output for internal Oscillator amplifier.
Table 12-7
shown in
Table 12-7.
Table 12-8.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 12-5 on page
and
0
PC7/ICP1/INT4/CLK0
0
0
0
0
0
INT4 ENABLE
1
INT4 INPUT
–
Overriding Signals for Alternate Functions in PC7..PC4
Overriding Signals for Alternate Functions in PC2..PC0
PC2/PCINT11
0
0
0
0
0
0
PCINT11 ENABLE
1
PCINT11 INPUT
–
Table 12-8
relate the alternate functions of Port C to the overriding signals
72.
PC6/PCINT8/
OC1A
0
0
0
0
OC1A ENABLE
OC1A
PCINT8 ENABLE
1
PCINT8 INPUT
–
PC1/RESET/dW
0
0
0
0
0
0
0
0
–
–
ATmega8U2/16U2/32U2
PC5/PCINT9/
OC1B
0
0
0
0
OC1B ENABLE
OC1B
PCINT9 ENABLE
1
PCINT9 INPUT
–
PC0/XTAL2
0
0
0
0
0
0
0
0
–
–
PC4/PCINT10
0
0
0
0
0
0
PCINT10 ENABLE
1
PCINT10 INPUT
–
78
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