ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 106
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10.13.1.4
10.13.1.5
106
ADD
SUBS
RSB
ADCHI
SAM3S Preliminary
Condition flags
Examples
R2, R1, R3
R8, R6, #240
R4, R4, #1280
R11, R0, R3
When Rd is PC in the ADD{cond} PC, PC, Rm instruction:
If S is specified, these instructions update the N, Z, C and V flags according to the result.
• Rd can be SP only in ADD and SUB, and only with the additional restrictions:
• Rn can be SP only in ADD and SUB
• Rd can be PC only in the ADD{cond} PC, PC, Rm instruction where:
• with the exception of the ADD{cond} PC, PC, Rm instruction, Rn can be PC only in ADD and
• bit[0] of the value written to the PC is ignored
• a branch occurs to the address created by forcing bit[0] of that value to 0.
SUB, and only with the additional restrictions:
– Rn must also be SP
– any shift in Operand2 must be limited to a maximum of 3 bits using LSL
– you must not specify the S suffix
– Rm must not be PC and must not be SP
– if the instruction is conditional, it must be the last instruction in the IT block
– you must not specify the S suffix
– the second operand must be a constant in the range 0 to 4095.
–
– When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded
– If you want to generate the address of an instruction, you have to adjust the constant
to b00 before performing the calculation, making the base address for the calculation
word-aligned.
based on the value of the PC. ARM recommends that you use the ADR instruction
instead of ADD or SUB with Rn equal to the PC, because your assembler
automatically calculates the correct constant for the ADR instruction.
; Sets the flags on the result
; Subtracts contents of R4 from 1280
; Only executed if C flag set and Z
; flag clear
6500C–ATARM–8-Feb-11
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