ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 179
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10.21.10 System Handler Control and State Register
• USGFAULTENA
Usage fault enable bit, set to 1 to enable
• BUSFAULTENA
Bus fault enable bit, set to 1 to enable
• MEMFAULTENA
Memory management fault enable bit, set to 1 to enable
• SVCALLPENDED
SVC call pending bit, reads as 1 if exception is pending
• BUSFAULTPENDED
Bus fault exception pending bit, reads as 1 if exception is pending
• MEMFAULTPENDED
Memory management fault exception pending bit, reads as 1 if exception is pending
• USGFAULTPENDED
Usage fault exception pending bit, reads as 1 if exception is pending
• SYSTICKACT
SysTick exception active bit, reads as 1 if exception is active
• PENDSVACT
PendSV exception active bit, reads as 1 if exception is active
1.
2.
3.
6500C–ATARM–8-Feb-11
SVCALLPENDE
SVCALLAVCT
31
23
15
D
7
Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception.
Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to change the pending
Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status of
status of the exceptions.
the exceptions, but see the Caution in this section.
BUSFAULTPEND
ED
30
22
14
6
The SHCSR enables the system handlers, and indicates:
See the register summary in
ments are:
• the pending status of the bus fault, memory management fault, and SVC exceptions
• the active status of the system handlers.
MEMFAULTPEN
Reserved
Reserved
DED
29
21
13
5
(3)
(1)
USGFAULTPEND
28
20
12
ED
4
Table 10-30 on page 164
(2)
(3)
Reserved
(3)
USGFAULTACT
SYSTICKACT
(2)
27
19
11
3
(2)
USGFAULTENA
PENDSVACT
Reserved
for the SHCSR attributes. The bit assign-
26
18
10
2
(2)
SAM3S Preliminary
BUSFAULTENA
BUSFAULTACT
Reserved
25
17
9
1
MEMFAULTENA
MEMFAULTACT
MONITORACT
24
16
8
0
179
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