ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 695
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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33.7.3.8
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
Parity
The USART supports five parity modes selected by programming the PAR field in the Mode
Register (US_MR). The PAR field also enables the Multidrop mode, see
page
If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a num-
ber of 1s in the character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the
receiver parity checker counts the number of received 1s and reports a parity error if the sam-
pled parity bit does not correspond. If odd parity is selected, the parity generator of the
transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if
the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is
used, the parity generator of the transmitter drives the parity bit to 1 for all characters. The
receiver parity checker reports an error if the parity bit is sampled to 0. If the space parity is
used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The
receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 33-9
depending on the configuration of the USART. Because there are two bits to 1, 1 bit is added
when a parity is odd, or 0 is added when a parity is even.
Table 33-9.
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status
Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with
the RSTSTA bit to 1.
Character
696. Even and odd parity bit generation and error detection are supported.
A
A
A
A
A
shows an example of the parity bit for the character 0x41 (character ASCII “A”)
Parity Bit Examples
Figure 33-22
Hexa
0x41
0x41
0x41
0x41
0x41
illustrates the parity bit status setting and clearing.
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Binary
SAM3S Preliminary
SAM3S Preliminary
Parity Bit
None
1
0
1
0
“Multidrop Mode” on
Parity Mode
Space
None
Even
Mark
Odd
695
695
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