ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 589

• Manufacturer Part Number: ATSAM3S1BA-AU
• Description: IC MCU 32BIT 64KB FLASH 64LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S1BA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 10x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 47
• Ram Memory Size: 16KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Figure 30-7.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
(from master)
(from slave)
TXEMPTY
NPCS0
SPCK
TDRE
MOSI
RDRF
MISO
SPI_TDR
Write in
Status Register Flags Behavior
Figure 30-7
Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Reg-
ister) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved.
Figure 30-8
of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags
behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode with the
Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data.
The next pointer and counter are not used. The RDRF and TDRE are not shown because these
flags are managed by the PDC when using the PDC.
MSB
1
MSB
shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End
2
6
6
3
5
5
4
4
4
5
3
3
6
6
2
2
SAM3S Preliminary
SAM3S Preliminary
7
1
1
shift register empty
8
LSB
LSB
RDR read
589
589