ATSAM3S1BA-AU Atmel, ATSAM3S1BA-AU Datasheet - Page 62
ATSAM3S1BA-AU
Manufacturer Part Number
ATSAM3S1BA-AU
Description
IC MCU 32BIT 64KB FLASH 64LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S1BA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
47
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 10x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
47
Ram Memory Size
16KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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10.5.8
62
SAM3S Preliminary
Programming hints for the synchronization primitives
Software can use the synchronization primitives to implement a semaphores as follows:
The Cortex-M3 includes an exclusive access monitor, that tags the fact that the processor has
executed a Load-Exclusive instruction. If the processor is part of a multiprocessor system, the
system also globally tags the memory locations addressed by exclusive accesses by each
processor.
The processor removes its exclusive access tag if:
In a multiprocessor implementation:
For more information about the synchronization primitive instructions, see
on page 100
ANSI C cannot directly generate the exclusive access instructions. Some C compilers provide
intrinsic functions for generation of these instructions:
Table 10-8.
The actual exclusive access instruction generated depends on the data type of the pointer
passed to the intrinsic function. For example, the following C code generates the require
LDREXB operation:
Instruction
LDREX, LDREXH, or
LDREXB
STREX, STREXH, or
STREXB
CLREX
• Use a Load-Exclusive instruction to read from the semaphore address to check whether the
• If the semaphore is free, use a Store-Exclusive to write the claim value to the semaphore
• If the returned status bit from the second step indicates that the Store-Exclusive succeeded
• It executes a CLREX instruction
• It executes a Store-Exclusive instruction, regardless of whether the write succeeds.
• An exception occurs. This means the processor can resolve semaphore conflicts between
• executing a CLREX instruction removes only the local exclusive access tag for the processor
• executing a Store-Exclusive instruction, or an exception. removes the local exclusive access
semaphore is free.
address.
then the software has claimed the semaphore. However, if the Store-Exclusive failed, another
process might have claimed the semaphore after the software performed the first step.
different threads.
tags, and all global exclusive access tags for the processor.
1: No write was performed. This indicates that the value returned the first step might be out
of date. The software must retry the read-modify-write sequence,
__ldrex((volatile char *) 0xFF);
and
C compiler intrinsic functions for exclusive access instructions
“CLREX” on page
Intrinsic function
unsigned int __ldrex(volatile void *ptr)
int __strex(unsigned int val, volatile void *ptr)
void __clrex(void)
102.
“LDREX and STREX”
6500C–ATARM–8-Feb-11
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