AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 1021

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

41.6.17
Name:
Addresses: 0xFFFFEC4C [0], 0xFFFFEC74 [1], 0xFFFFEC9C [2], 0xFFFFECC4 [3], 0xFFFFECEC [4],
Access:
Reset:
• SIF: Source Interface Selection Field
00: The source transfer is done via AHB-Lite Interface 0.
01: The source transfer is done via AHB-Lite Interface 1.
10: Reserved.
11: Reserved.
• DIF: Destination Interface Selection Field
00: The destination transfer is done via AHB-Lite Interface 0.
01: The destination transfer is done via AHB-Lite Interface 1.
10: Reserved.
11: Reserved.
• SRC_PIP
0: Picture-in-Picture mode is disabled. The source data area is contiguous.
1: Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is
automatically increment of a user defined amount.
• DST_PIP
0: Picture-in-Picture mode is disabled. The Destination data area is contiguous.
1: Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address
is automatically incremented by a user-defined amount.
• SRC_DSCR
0: Source address is updated when the descriptor is fetched from the memory.
1: Buffer Descriptor Fetch operation is disabled for the source.
6438F–ATARM–21-Jun-10
AUTO
31
23
15
–
7
–
DMAC Channel x [x = 0..7] Control B Register
DMAC_CTRLBx [x = 0..7]
0xFFFFED14 [5], 0xFFFFED3C [6], 0xFFFFED64 [7]
Read-write
0x00000000
IEN
FC
30
22
14
–
6
–
29
21
13
5
DST_INCR
DIF
DST_DSCR
DST_PIP
28
20
12
4
27
19
11
–
–
–
3
–
26
18
10
–
–
–
2
–
AT91SAM9G45
25
17
–
9
–
1
SRC_INCR
SIF
SRC_DSCR
SRC_PIP
24
16
8
0
1021