AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 1105
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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45.6.2.6
6438F–ATARM–21-Jun-10
Dithering
Table 45-9.
The lookup table can be accessed by the host in R/W mode to allow the host to program and
check the values stored in the palette. It is mapped in the LCD controller configuration memory
map. The LUT is mapped as 16-bit half-words aligned at word boundaries, only word write
access is allowed (the 16 MSB of the bus are not used). For the detailed memory map, see
Table 45-16 on page
The lookup table contains 256 16-bit wide entries. The 256 entries are chosen by the program-
mer from the 2
For the structure of each LUT entry, see
Table 45-10. Lookup Table Structure in the Memory
In STN Monochrome, only the four most significant bits of the red value are used (16 gray
shades). In STN Color, only the four most significant bits of the blue, green and red value are
used (4096 colors).
In TFT mode, all the bits in the blue, green and red values are used. The LCDD unused bits are
tied to 0 when TFT palletized configurations are used (LCDD[18:16], LCDD[9:8], LCDD[2:0]).
The dithering block is used to generate the shades of gray or color when the LCD Controller is
used with an STN LCD Module. It uses a time-based dithering algorithm and Frame Rate Con-
trol method.
The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the dis-
play an appearance of multiple shades. In order to reduce the flicker noise caused by turning on
and off adjacent pixels at the same time, a time-based dithering algorithm is used to vary the
pattern of adjacent pixels every frame. This algorithm is expressed in terms of Dithering Pattern
registers (DP_i) and considers not only the pixel gray level number, but also its horizontal
coordinate.
STN Mono
STN Color
STN Color
Address
00
01
...
FE
FF
DISTYPE
Red_value_0[4:0]
Red_value_1[4:0]
Red_value_254[4:0]
Red_value_255[4:0]
Palette Configurations (Continued)
16
possible combinations.
1125.
Configuration
PIXELSIZE
4
1, 2, 4, 8
16
Table
Green_value_0[5:0]
Green_value_1[5:0]
Green_value_254[5:0]
Green_value_255[5:0]
Data Output [15:0]
45-10.
Palette
Non-palletized
Palletized
Non-palletized
AT91SAM9G45
Blue_value_0[4:0]
Blue_value_1[4:0]
Blue_value_254[4:0]
Blue_value_255[4:0]
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