AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 78
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Figure 12-8. Watchdog Reset
12.4.5
78
WDRPROC = 0
AT91SAM9G45
Reset State Priorities
Only if
periph_nreset
proc_nreset
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a
processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog
Reset, and the Watchdog is enabled by default and with a period set to a maximum.
When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset
controller.
The Reset State Manager manages the following priorities between the different reset sources,
given in descending order:
Particular cases are listed below:
(nrst_out)
• If WDRPROC = 1, only the processor reset is asserted.
• Backup Reset
• Wake-up Reset
• Watchdog Reset
• Software Reset
• User Reset
• When in User Reset:
• When in Software Reset:
RSTTYP
wd_fault
NRST
SLCK
MCK
– A watchdog event is impossible because the Watchdog Timer is being reset by the
– A software reset is impossible, since the processor reset is being activated.
– A watchdog event has priority over the current state.
– The NRST has no effect.
proc_nreset signal.
Freq.
Any
Any
Processor Startup
= 3 cycles
XXX
EXTERNAL RESET LENGTH
8 cycles (ERSTL=2)
0x2 = Watchdog Reset
6438F–ATARM–21-Jun-10
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