AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 778
AT91SAM9G45-CU-999
Manufacturer Part Number
AT91SAM9G45-CU-999
Description
IC MCU ARM9 APMC 324TFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9G45-EKES.pdf
(1218 pages)
Specifications of AT91SAM9G45-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
400MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
Peripherals
AC'97, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Size
64KB (64K x 8)
Program Memory Type
ROM
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
0.9 V ~ 1.1 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
324-TFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Part Number
Manufacturer
Quantity
Price
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36.8.7
36.8.7.1
6438F–ATARM–21-Jun-10
WRITE_MULTIPLE_BLOCK
One Block per Descriptor
3. Wait for XFRDONE in HSMCI_SR register.
1. Wait until the current command execution has successfully terminated.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Program HSMCI_DMA register with the following fields:
5. Issue a WRITE_MULTIPLE_BLOCK command.
6. Program the DMA Controller to use a list of descriptors. Each descriptor transfers one
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set with the starting address of
e. The DMAC_DADDRx register for channel x must be word aligned.
f.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
h. Program DMAC_CFGx register for channel x with the following field’s values:
a. Check that CMDRDY and NOTBUSY are asserted in HSMCI_SR.
– OFFSET field with dma_offset.
– CHKSIZE is user defined.
– DMAEN is set to true to enable DMAC hardware handshaking in the HSMCI. This bit
block of data. Block n of data is transferred with descriptor LLI(n).
was previously set to false.
reading the DMAC_EBCISR register.
the HSMCI_FIFO address.
Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZE must be set according to the value of HSMCI_DMA.CHKSIZE Field.
–BTSIZE is programmed with CEILING(block_length/4).
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
–Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and
DMA Controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
waiting for request.
AT91SAM9G45
778
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