AT91SAM9G45-CU-999 Atmel, AT91SAM9G45-CU-999 Datasheet - Page 774

• Manufacturer Part Number: AT91SAM9G45-CU-999
• Description: IC MCU ARM9 APMC 324TFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G45-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 400MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, MMC, SPI, SSC, UART/USART, USB
• Peripherals: AC'97, DMA, I²S, LCD, POR, PWM, WDT
• Number Of I /o: 160
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: ROM
• Ram Size: 128K x 8
• Voltage - Supply (vcc/vdd): 0.9 V ~ 1.1 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

36.8.5
6438F–ATARM–21-Jun-10
WRITE_SINGLE_BLOCK Operation using DMA Controller
1. Wait until the current command execution has successfully terminated.
2. Program the block length in the card. This value defines the value block_length.
3. Program the block length in the HSMCI configuration register with block_length value.
4. Program HSMCI_DMA register with the following fields:
5. Issue a WRITE_SINGLE_BLOCK command writing HSMCI_ARG then HSMCI_CMDR.
6. Program the DMA Controller.
a. Check that CMDRDY and NOTBUSY fields are asserted in HSMCI_SR
– OFFSET field with dma_offset.
– CHKSIZE is user defined and set according to DMAC_DCSIZE.
– DMAEN is set to true to enable DMA hardware handshaking in the HSMCI. This bit
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMAC transfer by
c. Program the channel registers.
d. The DMAC_SADDRx register for channel x must be set to the location of the
e. The DMAC_DADDRx register for channel x must be set with the starting address of
f.
g. Program DMAC_CTRLBx register for channel x with the following field’s values:
h. Program DMAC_CFGx register for channel x with the following field’s values:
was previously set to false.
reading the DMAC_EBCISR register.
source data. When the first data location is not word aligned, the two LSB bits
define the temporary value called dma_offset. The two LSB bits of
DMAC_SADDRx must be set to 0.
the HSMCI_FIFO address.
Program DMAC_CTRLAx register of channel x with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–DCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with CEILING((block_length + dma_offset) / 4), where
–DST_INCR is set to INCR, the block_length value must not be larger than the
–SRC_INCR is set to INCR.
–FC field is programmed with memory to peripheral flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1 (descriptor fetch is disabled).
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the
–FIFOCFG defines the watermark of the DMAC channel FIFO.
–DST_H2SEL is set to true to enable hardware handshaking on the destination.
–DST_PER is programmed with the hardware handshaking ID of the targeted
the ceiling function is the function that returns the smallest integer not less than
x.
HSMCI_FIFO aperture.
DMA controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
AT91SAM9G45
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