ATMEGA2561-16AU Atmel, ATMEGA2561-16AU Datasheet - Page 343

• Manufacturer Part Number: ATMEGA2561-16AU
• Description: IC AVR MCU 256K 16MHZ 64TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA2561-16AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 6
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRZ541, ATAVRRAVEN, ATAVRRZUSBSTICK, ATAVRRZ201
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

29.7.5
2549M–AVR–09/10
Programming the EEPROM
K. End Page Programming
1. 1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals are
Figure 29-2. Addressing the Flash Which is Organized in Pages
Note:
Figure 29-3. Programming the Flash Waveforms
Note:
The EEPROM is organized in pages, see
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
reset.
RESET +12V
RDY/BSY
PAGEL
XTAL1
PCPAGE and PCWORD are listed in
DATA
1. “XX” is don’t care. The letters refer to the programming description above.
XA1
XA0
BS1
BS2
WR
OE
PROGRAM MEMORY
0x10
PROGRAM
COUNTER
A
PAGE
ADDR. LOW
PAGE ADDRESS
WITHIN THE FLASH
B
PCMSB
DATA LOW
C
PCPAGE
DATA HIGH
ATmega640/1280/1281/2560/2561
D
XX
E
ADDR. LOW
Table 29-7 on page
B
PAGEMSB
PCWORD
Table 29-8 on page
DATA LOW
C
WORD ADDRESS
WITHIN A PAGE
(1)
F
DATA HIGH
D
INSTRUCTION WORD
XX
E
338.
PAGE
ADDR. HIGH
G
(Note:)
338. When programming the
ADDR. EXT.H
H
I
XX
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
343