P89CV51RD2FBC,557 NXP Semiconductors, P89CV51RD2FBC,557 Datasheet - Page 15

• Manufacturer Part Number: P89CV51RD2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RD2FBC,557

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4257; 935284103557; P89CV51RD2FBC

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.2.2 Dual data pointers
The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1
determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is
selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data
pointers can be accomplished by a single INC instruction on AUXR1; see
Fig 4.
2FFH
000H
Internal and external data memory structure
2FFH
000H
EXPANDED RAM
ADDRESSING)
EXPANDED
(INDIRECT
768 B
RAM
Rev. 03 — 25 August 2009
FFFFH
0300H
FFH
7FH
80H
00H
P89CV51RB2/RC2/RD2
INTERNAL RAM
INTERNAL RAM
(INDIRECT AND
ADDRESSING)
ADDRESSING)
ADDRESSING)
LOWER 128 B
UPPER 128 B
EXTRAM = 0
EXTERNAL
(INDIRECT
(INDIRECT
MEMORY
DIRECT
DATA
FFFFH
0000H
FFH
80H
80C51 with 1 kB RAM, SPI
REGISTERS (SFRs)
ADDRESSING)
ADDRESSING)
EXTERNAL
FUNCTION
(INDIRECT
EXTRAM = 1
MEMORY
SPECIAL
(DIRECT
DATA
© NXP B.V. 2009. All rights reserved.
Figure
002aaa517
5.
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