P89CV51RD2FBC,557 NXP Semiconductors, P89CV51RD2FBC,557 Datasheet - Page 28

• Manufacturer Part Number: P89CV51RD2FBC,557
• Description: IC 80C51 MCU FLASH 64K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Cr

Specifications of P89CV51RD2FBC,557

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: P89CV5x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Cpu Family: 89C
• Device Core: 80C51
• Device Core Size: 8b
• Frequency (max): 40MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 44
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4257; 935284103557; P89CV51RD2FBC

NXP Semiconductors
P89CV51RB2_RC2_RD2_3
Product data sheet
6.4.1 Mode 0
Table 17.
Putting either timer into Mode 0 makes it look like an 8048 timer, which is an 8-bit counter
with a fixed divide-by-32 prescaler.
In this mode, the timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the timer interrupt flag TFn. The count input is enabled to the
timer when TRn = 1 and either GATE = 0 or INTn = 1. (Setting GATE = 1 allows the timer
to be controlled by external input INTn, to facilitate pulse width measurements). TRn is a
control bit in the special function register TCON
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1; see
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Bit
7
6
5
4
3
2
1
0
Fig 7.
INTn pin
TnGate
Tn pin
osc/6
TRn
Timer/counter 0 or 1 in Mode 0 (13-bit counter)
Symbol
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TCON - Timer/Counter control register (address 88H) bit description
Description
Timer 1 overflow Flag. Set by hardware on timer/counter overflow. Cleared
by hardware when the processor vectors to Timer 1 interrupt routine, or by
software.
Timer 1 Run control bit. Set/cleared by software to turn timer/counter 1
on/off.
Timer 0 overflow Flag. Set by hardware on timer/counter overflow. Cleared
by hardware when the processor vectors to Timer 0 interrupt routine, or by
software.
Timer 0 Run control bit. Set/cleared by software to turn timer/counter 0
on/off.
Interrupt 1 Edge flag. Set by hardware when external interrupt 1
edge/LOW-state is detected. Cleared by hardware when the interrupt is
processed, or by software.
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/LOW-state that triggers external interrupt 1.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/LOW-state is detected. Cleared by hardware when the interrupt is
processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/LOW-state that triggers external interrupt 0.
Rev. 03 — 25 August 2009
C/T = 0
C/T = 1
Figure 7
P89CV51RB2/RC2/RD2
control
shows Mode 0 operation.
(Table
(5-bits)
TLn
17). The GATE bit is in the TMOD
(8-bits)
THn
Figure
80C51 with 1 kB RAM, SPI
overflow
7. There are two
© NXP B.V. 2009. All rights reserved.
TFn
002aaa519
interrupt
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