ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 37
ST7FLITEUS5B6
Manufacturer Part Number
ST7FLITEUS5B6
Description
MCU 8BIT 1KB FLASH 128KB 8-DIP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet
1.STEVAL-IFS006V1.pdf
(136 pages)
Specifications of ST7FLITEUS5B6
Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
5
Program Memory Size
1KB (1K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Data Converters
A/D 5x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Controller Family/series
ST7
No. Of I/o's
5
Ram Memory Size
128Byte
Cpu Speed
8MHz
No. Of Timers
2
Rohs Compliant
Yes
For Use With
497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
497-5636-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST7FLITEUS5B6
Manufacturer:
STMicroelectronics
Quantity:
8
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ST7LITEUS2, ST7LITEUS5
6.4.5
6.5
6.5.1
6.5.2
Internal watchdog reset
The reset sequence generated by a internal watchdog counter overflow is shown in
Figure
Starting from the watchdog counter underflow, the device RESET pin acts as an output that
is pulled low during at least t
Figure 13. Reset sequences
Register description
Multiplexed I/O Reset Control register 1 (MUXCR1)
Reset value: 0000 0000 (00h)
Multiplexed I/O Reset Control register 0 (MUXCR0)
Reset value: 0000 0000 (00h)
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
MIR15
MIR7
V
V
IT+(LVD)
IT-(LVD)
7
7
13.
Bits 15:0 MIR[15:0]
V
Run
DD
MIR14
MIR6
ACTIVE PHASE
RESET
LVD
MIR13
MIR5
w(RSTL)out
t
Run
h(RSTL)in
.
MIR4
MIR12
Read / Write once
Read / Write once
WATCHDOG UNDERFLOW
ACTIVE
PHASE
EXTERNAL
RESET
MIR3
MIR11
INTERNAL RESET (64 T
VECTOR FETCH
Supply, reset and clock management
Run
ACTIVE
PHASE
WATCHDOG
RESET
t
w(RSTL)out
MIR2
MIR10
CPU
)
Run
MIR1
MIR9
MIR0
MIR8
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