ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 40

• Manufacturer Part Number: ST7FLITEUS5B6
• Description: MCU 8BIT 1KB FLASH 128KB 8-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEUS5B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: ST7
• No. Of I/o's: 5
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: 497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: 497-5636-5

Interrupts
7.2
Caution:
7.3
Note:
40/136
External interrupts
External interrupt vectors can be loaded into the PC register if the corresponding external
interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the
Halt low power mode.
The external interrupt polarity is selected through the miscellaneous register or interrupt
register (if available).
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies
to the ei source. In case of a NANDed source (as described in the I/O ports section), a low
level on an I/O pin, configured as input with interrupt, masks the interrupt request even in
case of rising-edge sensitivity.
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●
●
If any of these two conditions is false, the interrupt is latched and thus remains pending.
Clearing an interrupt request is done by:
●
●
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
Figure 14. Interrupt processing flowchart
The I bit of the CC register is cleared.
The corresponding enable bit is set in the control register.
Writing “0” to the corresponding bit in the status register or
Access to the status register while the flag is set followed by a read or write of an
associated register.
FROM RESET
EXECUTE INSTRUCTION
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
FETCH NEXT INSTRUCTION
N
I BIT SET?
IRET?
Y
Y
N
LOAD PC FROM INTERRUPT VECTOR
N
ST7LITEUS2, ST7LITEUS5
STACK PC, X, A, CC
INTERRUPT
PENDING?
SET I BIT
Y