ST7FLITEUS5B6 STMicroelectronics, ST7FLITEUS5B6 Datasheet - Page 46

• Manufacturer Part Number: ST7FLITEUS5B6
• Description: MCU 8BIT 1KB FLASH 128KB 8-DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITEUS5B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 1KB (1K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Data Converters: A/D 5x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: ST7
• No. Of I/o's: 5
• Ram Memory Size: 128Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Rohs Compliant: Yes
• For Use With: 497-6403 - BOARD EVAL 8BIT MICRO + TDE1708497-6407 - BOARD EVAL FOR VACUUM CLEANER497-5861 - EVAL BRD POWER MOSFET/8PIN MCU497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5515 - EVAL BOARD PHASE CTRL DIMMER497-5049 - KIT STARTER RAISONANCE ST7FLITE497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Other names: 497-5636-5

Interrupts
7.4.3
7.4.4
46/136
Low power modes
Table 11.
Interrupts
The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit
(AVDIE) is set and the interrupt mask in the CC register is reset (RIM instruction).
Table 12.
Register description
System Integrity (SI) Control/Status register (SICSR)
Reset value: 0000 0x00 (0xh)
Wait
Halt
AVD event
7
0
Mode
Bits 6:5 CR[1:0] RC Oscillator Frequency Adjustment bits
Bits 4:3 Reserved, must be kept cleared.
Interrupt Event
Bit 7 Reserved, must be kept cleared.
Description of low power modes
Description of interrupt events
CR1
These bits, as well as CR[9:2] bits in the RCCR register must be written
immediately after reset to adjust the RC oscillator frequency and to obtain the
required accuracy. Refer to
page
No effect on SI. AVD interrupts cause the device to exit from Wait mode.
The SICSR register is frozen.
The AVD remains active but the AVD interrupt cannot be used to exit from Halt
mode.
28.
CR0
0
Event flag
AVDF
Section 6.2: Internal RC oscillator adjustment on
Read/write
0
Description
control bit
Enable
AVDIE
LVDRF
ST7LITEUS2, ST7LITEUS5
Exit from
Wait
Yes
AVDF
Exit from
Halt
AVDIE
No
0