EZ80F93AZ020EC00TR Zilog, EZ80F93AZ020EC00TR Datasheet - Page 119

IC ACCLAIM MCU 64KB 100LQFP

EZ80F93AZ020EC00TR

Manufacturer Part Number
EZ80F93AZ020EC00TR
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Datasheets

Specifications of EZ80F93AZ020EC00TR

Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F93AZ020EC00T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EZ80F93AZ020EC00TR
Manufacturer:
Zilog
Quantity:
10 000
PS015313-0508
Table 54. UART Transmit Holding Registers(UART0_THR = 00C0h, UART1_THR =
UART Receive Buffer Register
The bits in this register reflect the data received. If less than eight bits are programmed for
receive, the lower bits of the byte reflect the bits received whereas upper unused bits are 0.
The receive FIFO is mapped at this address. If the FIFO is disabled, this buffer is only one
byte deep.
These registers share the same address space as the UARTx_THR and UARTx_BRG_L
registers. See
Table 55. UART Receive Buffer Registers(UART0_RBR = 00C0h, UART1_RBR =
00 D0h)
00D0h)
Bit
Reset
CPU Access
Note: W = Write only.
Bit
Position
[7:0]
T
Bit
Reset
CPU Access
Note: R = Read only.
Bit
Position
[7:0]
R
x
x
D
D
Table
Value
00h–
FFh
Value
00h–
FFh
55.
Description
Transmit data byte.
Description
Receive data byte.
W
X
X
R
7
7
W
X
X
R
6
6
W
R
X
X
5
5
Universal Asynchronous Receiver/Transmitter
W
R
X
X
4
4
W
R
X
X
3
3
Product Specification
W
R
X
X
2
2
eZ80F92/eZ80F93
W
X
X
R
1
1
W
X
X
R
0
0
112

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