EZ80F93AZ020EC00TR Zilog, EZ80F93AZ020EC00TR Datasheet - Page 139

• Manufacturer Part Number: EZ80F93AZ020EC00TR
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020EC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: EZ80F93AZ020EC00T

PS015313-0508
(CPHA bit = 0) Data Out
(CPHA bit = 1) Data Out
ENABLE (To Slave)
SCK (CPOL bit = 0)
SCK (CPOL bit = 1)
Sample Input
Sample Input
When the Clock Phase bit (CPHA) is set to 0, the shift clock is the logical OR of SS with
SCK. In this clock phase mode, SS must go High between successive characters in an SPI
message. When CPHA is set to 1, SS can remain Low for several SPI characters. In cases
where there is only one SPI slave, its SS line could be tied Low as long as CPHA is set
to 1. See (SPI_CTL) on page 136 for more information about CPHA.
Serial Clock
The Serial Clock (SCK) is used to synchronize data movement both in and out of the
device through its MOSI and MISO pins. The master and slave are each capable of
exchanging a byte of data during a sequence of eight clock cycles. As SCK is generated by
the master, the SCK pin becomes an input on a slave device. The SPI contains an internal
divide-by-two clock divider. In MASTER mode, the SPI serial clock is one-half the fre-
quency of the clock signal created by the SPI’s Baud Rate Generator.
As displayed in
chosen by using control bits CPOL and CPHA in the SPI Control register. See the SPI
Control Register (SPI_CTL) on page 136. Both the master and slave must operate with the
identical timing, clock polarity (CPOL), and clock phase (CPHA). The master device
always places data on the MOSI line a half-cycle before the clock edge (SCK signal) so
that the slave device latches the data.
Figure 31
MSB
MSB
1
Figure 31. SPI Timing
and
6
6
Table 71
2
Number of Cycles on the SCK Signal
5
5
3
on page 133, four possible timing relations may be
4
4
4
3
3
5
2
2
6
Product Specification
1
Serial Peripheral Interface
1
7
eZ80F92/eZ80F93
LSB
LSB
8
132