EZ80F93AZ020EC00TR Zilog, EZ80F93AZ020EC00TR Datasheet - Page 70

• Manufacturer Part Number: EZ80F93AZ020EC00TR
• Description: IC ACCLAIM MCU 64KB 100LQFP
• Manufacturer: Zilog
• Series: eZ80® Acclaim!®r

Specifications of EZ80F93AZ020EC00TR

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 24
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Other names: EZ80F93AZ020EC00T

Table 20. Motorola Bus Mode Read States
PS015313-0508
STATE S0
STATE S1
STATE S2
STATE S3
Motorola Bus Mode
The Read cycle starts in state S0. The CPU drives R/W High to identify a Read cycle.
During state S3, no bus signals are altered.
Entering state S1, the CPU drives a valid address on the address bus, ADDR[23:0].
On the rising edge of state S2, the CPU asserts AS and DS.
Chip selects configured for Motorola bus mode modify the CPU bus signals to duplicate
an eight-state memory transfer similar to that found on Motorola-style microcontrollers.
The bus signals (and eZ80F92 I/O pins) are mapped as displayed in
During Write operations, the Motorola bus mode employs eight states (S0, S1, S2, S3, S4,
S5, S6, and S7) as listed in
eZ80 Bus Mode
Signals (Pins)
ADDR[23:0]
DATA[7:0]
INSTRD
MREQ
IORQ
WAIT
WR
RD
Figure 16. Motorola Bus Mode Signal and Pin Mapping
Table
Bus Mode
Controller
20.
Motorola Bus
Signal Equvalents
AS
DS
R/W
DTACK
MREQ
IORQ
ADDR[23:0]
DATA[7:0]
Chip Selects and Wait States
Product Specification
Figure
eZ80F92/eZ80F93
16.
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