EZ80F93AZ020EC00TR Zilog, EZ80F93AZ020EC00TR Datasheet - Page 180
EZ80F93AZ020EC00TR
Manufacturer Part Number
EZ80F93AZ020EC00TR
Description
IC ACCLAIM MCU 64KB 100LQFP
Manufacturer
Zilog
Series
eZ80® Acclaim!®r
Specifications of EZ80F93AZ020EC00TR
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-
Other names
EZ80F93AZ020EC00T
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Manufacturer
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PS015313-0508
Table 96. ZDI BREAK Control Register(ZDI_BRK_CTL = 10h in the ZDI Write Only
Register Address Space)
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
7
brk_next
6
brk_addr3
5
brk_addr2
4
brk_addr1
3
brk_addr0
Value Description
0
1
0
1
0
1
0
1
0
1
W
7
0
The ZDI BREAK on the next CPU instruction is disabled.
Clearing this bit releases the CPU from its current BREAK
condition.
The ZDI BREAK on the next CPU instruction is enabled.
The CPU can use multibyte Op Codes and multibyte
operands. BREAK points only occur on the first Op Code in
a multibyte Op Code instruction. If the ZCL pin is High and
the ZDA pin is Low at the end of RESET, this bit is set to 1
and a BREAK occurs on the first instruction following the
RESET. This bit is set automatically during ZDI BREAK on
address match. A BREAK can also be forced by writing a 1
to this bit.
The ZDI BREAK, upon matching BREAK address 3, is
disabled.
The ZDI BREAK, upon matching BREAK address 3, is
enabled.
The ZDI BREAK, upon matching BREAK address 2, is
disabled.
The ZDI BREAK, upon matching BREAK address 2, is
enabled.
The ZDI BREAK, upon matching BREAK address 1, is
disabled.
The ZDI BREAK, upon matching BREAK address 1, is
enabled.
The ZDI BREAK, upon matching BREAK address 0, is
disabled.
The ZDI BREAK, upon matching BREAK address 0, is
enabled.
W
6
0
W
5
0
W
4
0
W
3
0
Product Specification
W
2
0
eZ80F92/eZ80F93
Zilog Debug Interface
W
1
0
W
0
0
173
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