MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 224

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Multiply-Accumulate Unit (MAC)
cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some
variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal
transforms may have more demanding speed requirements beyond scope of any processor architecture and
may require full DSP implementation.
To balance speed, size, and functionality, the ColdFire MAC is optimized for a small set of operations that
involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for
single-cycle pipelined operations with a possible accumulation after product generation. This functionality
is common in many signal processing applications. The ColdFire core architecture is also modified to
allow an operand to be fetched in parallel with a multiply, increasing overall performance for certain DSP
operations.
Consider a typical filtering operation where the filter is defined as in
Here, the output y(i) is determined by past output values and past input values. This is the general form of
an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting
coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies
and product summing. To show this point, reduce
Equation
9.2
The following table and sections explain the MAC registers:
9.2.1
The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and overflow condition flags are also provided.
9-2
1
Read: 0xE4
Write: 0xC4
Read: 0xE5
Write: 0xC5
Read: 0xE6
Write: 0xC6
For more information see
BDM
1
9-2, in which the accumulated sum is a past data values and coefficients sum.
Memory Map/Register Definition
MAC Status Register (MACSR)
i ( )
MAC Status Register (MACSR)
MAC Address Mask Register (MASK)
Accumulator (ACC)
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 1.11
=
k
∑
=
3
0
b k ( )x i k
Chapter 26, “Version 1 ColdFire Debug (CF1_DEBUG).”
(
y i ( )
–
)
Register
=
=
k
N 1
∑
b 0 ( )x i ( )
–
=
Table 9-1. MAC Memory Map
1
a k ( )y i k
(
+
b 1 ( )x i 1
–
)
Equation 9-1
+
(
k
N 1
∑
–
=
–
0
b k ( )x i k
)
+
b 2 ( )x i 2
(
Width
(bits)
to a simple, four-tap FIR filter, shown in
–
16
32
8
(
)
–
Equation
Access
)
R/W
R/W
R/W
+
b 3 ( )x i 3
Reset Value
(
9-1.
Undefined
0xFFFF
–
0x00
Freescale Semiconductor
Section/Page
9.2.1/9-2
9.2.2/9-4
9.2.3/9-5
Eqn. 9-1
Eqn. 9-2