MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 357

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.4.3
All received Addresses can be requested in 7-bit or 10-bit address. IIC Address Register 1, which contains
IIC primary slave address, always participates the address matching process. If the GCAEN bit is set,
general call will participate the address matching process. If the ALERTEN bit is set, alert response will
participate the address matching process. If SIICAEN bit is set, the IIC Address Register 2 will participate
the address matching process.
When the IIC responds to one of above mentioned address, it acts as a slave-receiver and the IAAS bit is
set after the address cycle. Software need to read the IICD register after the first byte transfer to determine
which the address is matched.
15.4.4
SMBus provides a control bus for system and power management related tasks. A system may use SMBus
to pass messages to and from devices instead of tripping individual control lines. Removing the individual
control lines reduces pin count. Accepting messages ensures future expandability.With System
Management Bus, a device can provide manufacturer information, tell the system what its model/part
number is, save its state for a suspend event, report different types of errors, accept control parameters, and
return its status.
15.4.4.1
The T
clock low indefinitely or a master is intentionally trying to drive devices off the bus. It is highly
recommended that a slave device release the bus (stop driving the bus and let SCL and SDA float high)
when it detects any single clock held low longer than T
condition should reset their communication and be able to receive a new START condition in no later than
T
SMBus defines a clock low time-out, T
low extend time for a slave device and specifies T
a master device.
15.4.4.1.1
If the SCL line is held low by a slave device on the bus, no further communication is possible.
Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this
problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle
held low longer than a “timeout” value condition. Devices that have detected the timeout condition must
reset the communication. When active master, if the IIC detects that SMBCLK low has exceeded the value
of T
process. When slave, upon detection of the T
and be able to receive a new START condition.
Freescale Semiconductor
TIMEOUT,MAX
TIMEOUT,MIN
TIMEOUT,MIN
Address Matching
System Management Bus Specification
Timeouts
.
SCL Low Timeout
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
it must generate a stop condition within or after the current data byte in the transfer
parameter allows a master or slave to conclude that a defective device is holding the
TIMEOUT
TIMEOUT,MIN
of 35 ms and specifies T
LOW: MEXT
TIMEOUT,MIN
condition, the IIC shall reset its communication
as the cumulative clock low extend time for
. Devices that have detected this
LOW: SEXT
as the cumulative clock
Inter-Integrated Circuit (IIC)
15-19