MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 301

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

13.3.8
The SPI Clear Interrupt register has 4 bits dedicated for clearing the interrupts. Writing 1 to these bits clears
the respective interrupts if INTCLR bit in SPIxCR3 is set.
It also have 2 bits to indicate the transmit fifo and receive fifo overrun conditions. When receive fifo is full
and a data is received RXFOF flag is set. Similarily when transmit fifo is full and write happens to SPIDR
TXFOF is set. These flags gets cleared when a read happens to this register with the flags set.
There are two more bits to indicate the error flags. These flags gets set when due to some spurious reasons
entries in fifo becomes greater than 8. At this point all the flags in status register gets reset and entries in
FIFO are flushed with respective error flags set. These flags are cleared when a read happen at SPIxCI with
the error flags set.
Note: Bits [7:4] are readonly bits. These bits gets cleared when a read happens to this register with the flags set. Bits [3:0] are
Freescale Semiconductor
RNFULLIEN
FIFOMODE
TNEARIEN
INTCLR
Reset
Field
clear interrupts bits which clears the interrupts by writing 1 to respective bits. Reading these bits always return 0.
3
2
1
0
W
R
TXFERR
SPI Clear Interrupt Register (SPIxCI)
Interrupt Clearing Mechanism Select - This bit selects the mechanism by which SPRF, SPTEF, TNEAREF,
RNFULLF interrupts gets cleared.
0 Interrupts gets cleared when respective flags gets cleared depending on the state of FIFOs
1 Interrupts gets cleared by writing to the SPIxCI respective bits.
Transmit FIFO Nearly Empty Interrupt Enable — Writing to this bit enables the SPI to interrupt the CPU when
the TNEAREF flag is set. This is an additional interrupt on the SPI and will only interrupt the CPU if SPTIE in the
SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE=0.
0 No interrupt on Transmit FIFO Nearly Empty Flag being set.
1 Enable interrupts on Transmit FIFO Nearly Empty Flag being set.
Receive FIFO Nearly Full Interrupt Enable — Writing to this bit enables the SPI to interrupt the CPU when the
RNEARFF flag is set. This is an additional interrupt on the SPI and will only interrupt the CPU if SPIE in the
SPIxC1 register is also set. This bit is ignored and has no function if FIFOMODE = 0.
0 No interrupt on RNEARFF being set.
1 Enable interrupts on RNEARFF being set.
SPI FIFO Mode Enable — This bit enables the SPI to utilise a 64-bit FIFO (8bytes 4 16-bit words) for both
transmit and receive buffers.
0 Buffer mode disabled.
1 Data available in the receive data buffer.
0
7
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
= Unimplemented or Reserved
RXFERR
0
6
Table 13-9. SPIxC3 Register Field Descriptions
TXFOF
0
5
RXFOF
0
4
Description
TNEAREFCI RNFULLFCI
3
0
16-Bit Serial Peripheral Interface (SPI16)
0
2
SPTEFCI
0
1
SPRFCI
0
0
13-15