MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 352

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Inter-Integrated Circuit (IIC)
15.4.1
The IIC bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices
connected to it must have open drain or open collector outputs. A logic AND function is exercised on both
lines with external pullup resistors. The value of these resistors is system dependent.
Normally, a standard communication is composed of four parts:
The STOP signal should not be confused with the CPU STOP instruction. The IIC bus system
communication is described briefly in the following sections and illustrated in
15.4.1.1
When the bus is free; i.e., no master device is engaging the bus (both SCL and SDA lines are at logical
high), a master may initiate communication by sending a START signal. As shown in
START signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the
beginning of a new data transfer (each data transfer may contain several bytes of data) and brings all slaves
out of their idle states.
15-14
SDA
SCL
SDA
SCL
•
•
•
•
SIGNAL
SIGNAL
START
START
START signal
Slave address transmission
Data transfer
STOP signal
MSB
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
1
IIC Protocol
START Signal
2
2
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
CALLING ADDRESS
CALLING ADDRESS
3
3
4
4
5
5
6
6
Figure 15-13. IIC Bus Transmission Signals
7
7
READ/
WRITE
READ/
WRITE
LSB
LSB
8
8
ACK
ACK
BIT
BIT
9
9
XX
REPEATED
SIGNAL
XXX
START
MSB
MSB
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
D7
1
1
D6
2
2
NEW CALLING ADDRESS
D5
3
3
DATA BYTE
D4
4
4
D3
5
5
D2
6
6
D1
7
7
Figure
READ/
WRITE
LSB
LSB
D0
8
8
Freescale Semiconductor
ACK
BIT
NO
ACK
BIT
NO
9
9
15-13.
Figure
SIGNAL
SIGNAL
STOP
STOP
15-13, a