MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 385

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 17
Independent Real Time Clock (IRTC)
17.1
The IRTC, independent real time clock, provides the functionality of a basic RTC like time keeping and
calendaring and additionally provides protection against tampering, spurious memory/register updates
and battery operation. It can additionally compensate the 1 Hz clock against variations in 32 kHz clock in
oscillator due to crystal or temperature. A standby RAM is provided if the CPU wants to store any data
that has to be retained when in battery operation mode.
17.1.1
The IRTC power supply source depends on the MCU operation mode and the LVD configuration.
Freescale Semiconductor
Introduction
IRTC Power Supply Source
The IRTC Configuration Data Register (IRTC_CFG_DATA) bits [7:1] are
reserved in MCF51EM256 family devices, and must be written as 0's. Bit 0
(CFG0) is used as the configuration bit to control the address mapping of the
two flash blocks. Refer to section
MCF51EM256 series have only one tamper pin. Further reference to a
different number of tamper pins must be disregarded.
The IRTC features a protection mechanism to protect against spurious
writes into the IRTC registers by any run-away code. On power-on reset a
15 s window is allowed for the CPU to configure the IRTC after which the
registers are locked. Refer to
The IRTC tamper interrupt is enabled after reset (IRTC_IER register, bit
TMPR = 1). A POR generates a tamper interrupt request by setting the bit
TMPR in the IRTC_ISR register.
Year & Month Alarm (IRTC_ALM_YRMON), Days Alarm
(IRTC_ALM_DAYS), Hours and Minutes Alarm (IRTC_ALM_HM),
Seconds Alarm (IRTC_ALM_SEC), Status (IRTC_STATUS), Interrupt
Status (IRTC_ISR) bits [15:1], Interrupt Enable (IRTC_IER) bits [15:1] and
Configuration Data Registers (IRTC_CFG_DATA) are reset by IRTC soft
reset or IRTC power-on reset. All other registers are reset by IRTC power-on
reset. IRTC power-on reset occurs when V
above the POR rearm voltage.
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
Section 17.4,
NOTE
Section 3.4.2, “Dual Flash
DD
“Overview," for details.
or V
bat
applies a voltage
Controllers.”
17-1