MCF51EM128CLK Freescale Semiconductor, MCF51EM128CLK Datasheet - Page 81

• Manufacturer Part Number: MCF51EM128CLK
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF51EMr

Specifications of MCF51EM128CLK

• Core Processor: Coldfire V1
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LCD, LVD, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x16b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Processor Series: MCF51EM
• Core: ColdFire V1
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: RS-232, LIN
• Maximum Clock Frequency: 50 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: TWR-MCF51CN-KIT, TWR-SER, TWR-ELEV, TOWER
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
0x(FF)FF_E01E–
0x(FF)FF_E016–
0x(FF)FF_E026–
0x(FF)FF_FFDB
0x(FF)FF_FFDE
0x(FF)FF_E00C
0x(FF)FF_E00D
0x(FF)FF_E01C
0x(FF)FF_E01D
0x(FF)FF_FFCF
0x(FF)FF_FFD0
0x(FF)FF_FFD8
0x(FF)FF_FFD9
0x(FF)FF_FFDF
0x(FF)FF_E00E
0x(FF)FF_E00F
0x(FF)FF_E01A
0x(FF)FF_E01B
0x(FF)FF_E01F
0x(FF)FF_E010
0x(FF)FF_E011
0x(FF)FF_E012
0x(FF)FF_E013
0x(FF)FF_E014
0x(FF)FF_E015
0x(FF)FF_E017
0x(FF)FF_E018
0x(FF)FF_E019
0x(FF)FF_E020
0x(FF)FF_E021
0x(FF)FF_E022
0x(FF)FF_E023
0x(FF)FF_E024
0x(FF)FF_E025
Address
MCF51EM256 Series ColdFire Integrated Microcontroller Reference Manual, Rev. 8
PDBCH1DLYB
PDBCH2DLYB
PDBCH3DLYB
PDBCH4DLYB
PDBCH2DLYA
PDBCH3DLYA
PDBCH4DLYA
INTC_PL6P7
INTC_PL6P6
INTC_CFRC
PDBCH2CR
PDBCH3CR
PDBCH4CR
INTC_SFRC
INTC_WCR
INTC_FRC
Reserved
Reserved
Reserved
Reserved
Name
Table 3-3. Detailed Peripheral Memory Map (Sheet 21 of 22)
ERRA
ERRA
ERRA
Bit 7
ENB
—
—
—
0
0
0
0
0
0
0
0
ERRB
ERRB
ERRB
LVL1
—
—
—
6
0
0
0
0
0
0
0
0
LVL2
—
—
—
5
0
0
0
0
AOS
AOS
AOS
LVL3
—
—
—
4
0
0
0
0
DELAY[15:8]
DELAY[15:8]
DELAY[15:8]
DELAY[15:8]
DELAY[15:8]
DELAY[15:8]
DELAY[15:8]
RESERVED
RESERVED
DELAY[7:0]
DELAY[7:0]
DELAY[7:0]
DELAY[7:0]
DELAY[7:0]
DELAY[7:0]
DELAY[7:0]
LVL4
—
—
—
3
0
0
0
0
REQN
REQN
BOS
BOS
BOS
CLR
SET
LVL5
—
—
—
2
0
0
0
MASK
LVL6
ENA
ENA
ENA
—
—
—
1
0
0
0
Memory
LVL7
Bit 0
ENB
ENB
ENB
—
—
—
0
0
0
3-25