MCF5271CVM150J Freescale Semiconductor, MCF5271CVM150J Datasheet - Page 22
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MCF5271CVM150J
Manufacturer Part Number
MCF5271CVM150J
Description
IC MCU 166MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5271CVM150J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
97
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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25.6.7
26.1
26.1.1
26.1.2
26.1.3
26.2
26.2.1
26.2.1.1
26.2.2
26.2.3
26.2.4
26.2.5
26.2.6
26.2.7
26.2.8
26.2.9
26.2.10
26.3
26.3.1
26.3.2
26.3.3
26.3.3.1
26.3.3.2
26.3.3.3
26.3.3.4
26.3.3.5
26.3.3.6
26.4
26.4.1
26.4.2
26.4.2.1
26.4.2.2
26.4.2.3
26.4.3
26.4.4
26.4.5
xxii
Paragraph
Number
Introduction................................................................................................................... 26-1
Memory Map/Register Definition ................................................................................ 26-3
Functional Description................................................................................................ 26-13
Initialization/Application Information ........................................................................ 26-15
Arbitration Lost....................................................................................................... 25-16
Overview................................................................................................................... 26-1
Features..................................................................................................................... 26-1
Modes of Operation .................................................................................................. 26-2
MDHA Mode Register (MDMR) ............................................................................. 26-4
MDHA Control Register (MDCR) ........................................................................... 26-6
MDHA Command Register (MDCMR) ................................................................... 26-7
MDHA Status Register (MDSR) .............................................................................. 26-8
MDHA Interrupt Status & Mask Registers (MDISR and MDIMR) ...................... 26-10
MDHA Data Size Register (MDDSR).................................................................... 26-11
MDHA Input FIFO (MDIN)................................................................................... 26-12
MDHA Message Digest Registers 0 (MDx0) ......................................................... 26-12
MDHA Message Data Size Register (MDMDS).................................................... 26-12
MDHA Message Digest Registers 1 (MDx1) ......................................................... 26-13
MDHA Top Control................................................................................................ 26-14
FIFO........................................................................................................................ 26-14
MDHA Logic.......................................................................................................... 26-14
Performing a Standard HASH Operation ............................................................... 26-15
Performing a HMAC Operation Without the MACFULL Bit ............................... 26-15
Performing a SHA-1 EHMAC................................................................................ 26-17
Performing a MAC Operation With the MACFULL Bit ....................................... 26-18
Performing an NMAC ............................................................................................ 26-19
Invalid Modes ....................................................................................................... 26-6
Address Decoder................................................................................................. 26-14
Interface Control................................................................................................. 26-14
Auto-Padder........................................................................................................ 26-14
Hashing Engine................................................................................................... 26-14
Hashing Engine Control ..................................................................................... 26-15
Status Interrupt.................................................................................................... 26-15
Generation of Key with IPAD ............................................................................ 26-16
Generation of Key with OPAD........................................................................... 26-16
HMAC Hash ....................................................................................................... 26-17
Message Digest Hardware Accelerator (MDHA)
MCF5271 Reference Manual, Rev. 2
Contents
Chapter 26
Title
Freescale Semiconductor
Number
Page
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