MCF5271CVM150J Freescale Semiconductor, MCF5271CVM150J Datasheet - Page 434
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MCF5271CVM150J
Manufacturer Part Number
MCF5271CVM150J
Description
IC MCU 166MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5271CVM150J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
97
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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Queued Serial Peripheral Interface (QSPI) Module
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also
causes the value in QAR to increment.
Correspondingly, a read at QDR returns the data in the RAM at the address specified by
QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.
23.3.5 QSPI Address Register (QAR)
The QAR, shown in
write operations affect.
23.3.6 QSPI Data Register (QDR)
The QDR, shown in
writes all data from and to the QSPI RAM through this register.
23.3.7 Command RAM Registers (QCR0–QCR15)
The command RAM is accessed using the upper byte of QDR. The QSPI cannot modify
information in command RAM.
There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select
field enables external peripherals for transfer. The command field provides transfer operations.
23-14
Address
Address
Reset
Reset
W
W
R
R
15
15
0
0
0
The QAR does not wrap after the last queue entry within each section
of the RAM. The application software must handle address range
errors.
14
14
0
0
0
Figure
Figure
13
13
0
0
0
Figure 23-9. QSPI Data Register (QDR)
12
12
23-8, is used to specify the location in the QSPI RAM that read and
0
0
0
23-9, is used to access QSPI RAM indirectly. The CPU reads and
Figure 23-8. QSPI Address Register
11
11
0
0
0
MCF5271 Reference Manual, Rev. 2
10
10
0
0
0
IPSBAR + 0x00_0350
IPSBAR + 0x00_0354
0
0
0
9
9
NOTE
0
0
0
8
8
DATA
0
0
0
7
7
6
0
0
6
0
0
0
5
5
0
0
4
4
0
0
3
3
ADDR
Freescale Semiconductor
0
0
2
2
0
0
1
1
0
0
0
0
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