MCF5271CVM150J Freescale Semiconductor, MCF5271CVM150J Datasheet - Page 518
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MCF5271CVM150J
Manufacturer Part Number
MCF5271CVM150J
Description
IC MCU 166MHZ 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF527xr
Specifications of MCF5271CVM150J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
150MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
97
Program Memory Type
ROMless
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
196-MAPBGA
Processor Series
MCF527x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
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Random Number Generator (RNG)
27.3.4 RNG Core Engine
The Core Engine Block contains the logic used to generate random data. The logic within the Core
Engine contains the internal shift registers as well as the logic used to generate the two oscillator
based clocks. This logic is "brainless" and must be controlled by the Control Block. The Control
Block controls how the shift registers are configured as well as when the oscillator clocks are
turned on.
27.4
The intended general operation of the RNG is as follows:
27-6
1. Reset/initialize
2. Write to the RNG entropy register (optional).
3. Write to the RNG control register and set the interrupt mask, high assurance, and GO bits.
4. Poll RNG status register for FIFO level
5. Read available random data from RNG output FIFO
6. Repeat steps 3 and 4 as needed
Initialization/Application Information
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
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