MCF5271CVM150J Freescale Semiconductor, MCF5271CVM150J Datasheet - Page 495

• Manufacturer Part Number: MCF5271CVM150J
• Description: IC MCU 166MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5271CVM150J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

26.2
Table 26-1
Freescale Semiconductor
• MAC: A Message Authentication Code is a one-way function performed on a message with
— MD5: Message Digest 5 Algorithm defined by Ron Rivest of MIT Laboratory for
two user defined keys:
— HMAC—Hashed message authentication can be used with either the SHA-1 or MD5
— EHMAC—Enhanced Hashed message authentication can only be used with the SHA-1
Computer Science and RSA Data Security, INC.
algorithm defined in Federal Information Processing Standards Publication 198.
algorithm.
Memory Map/Register Definition
shows the MDHA memory map.
0x19_0048–
0x19_000C
0x19_001C
0x19_003C
0x19_007C
0x19_006F
0x19_0000
0x19_0004
0x19_0008
0x19_0010
0x19_0014
0x19_0020
0x19_0030
0x19_0034
0x19_0038
0x19_0040
0x19_0044
0x19_0070
0x19_0074
0x19_0078
0x19_0080
IPSBAR
Offset
Mnemonic
MDCMR
MDMDS
MDDSR
MDIMR
Table 26-1. MDHA Module Memory Map
MDISR
MDMR
MDCR
MDSR
MDA0
MDB0
MDC0
MDD0
MDE0
MDA1
MDB1
MDC1
MDD1
MDE1
MDIN
—
MCF5271 Reference Manual, Rev. 2
[31:24]
MDHA Interrupt Status Register
MDHA Interrupt Mask Register
Message Digest C0 Register
Message Digest D0 Register
Message Digest C1 Register
Message Digest D1 Register
Message Digest A0 Register
Message Digest B0 Register
Message Digest E0 Register
Message Data Size Register
Message Digest A1 Register
Message Digest B1 Register
Message Digest E1 Register
MDHA Input FIFO Register
MDHA Command Register
MDHA Data Size Register
MDHA Control Register
MDHA Status Register
MDHA Mode Register
[23:16]
Reserved
[15:8]
[7:0]
Memory Map/Register Definition
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
W
R
R
26-3