MCF5271CVM150J Freescale Semiconductor, MCF5271CVM150J Datasheet - Page 391

• Manufacturer Part Number: MCF5271CVM150J
• Description: IC MCU 166MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5271CVM150J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Functional Description
For internal loopback set RCR[LOOP] = 1 and RCR[DRT] = 0. ETXEN and ETXER will not
assert during internal loopback. During internal loopback, the transmit/receive data rate is higher
than in normal operation because the internal system clock is used by the transmit and receive
blocks instead of the clocks from the external transceiver. This will cause an increase in the
required system bus bandwidth for transmit and receive data being DMA’d to/from external
memory. It may be necessary to pace the frames on the transmit side and/or limit the size of the
frames to prevent transmit FIFO underrun and receive FIFO overflow.
For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver
for loopback.
19.3.14 Ethernet Error-Handling Procedure
The Ethernet controller reports frame reception and transmission error conditions using the FEC
RxBDs, the EIR register, and the MIB block counters.
19.3.14.1 Transmission Errors
19.3.14.1.1 Transmitter Underrun
If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All
remaining buffers for that frame are then flushed and closed. The UN bit is set in the EIR. The FEC
will then continue to the next transmit buffer descriptor and begin transmitting the next frame.
The “UN” interrupt will be asserted if enabled in the EIMR register.
19.3.14.1.2 Retransmission Attempts Limit Expired
When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are
flushed and closed, and the RL bit is set in the EIR. The FEC will then continue to the next transmit
buffer descriptor and begin transmitting the next frame.
The “RL” interrupt will be asserted if enabled in the EIMR register.
19.3.14.1.3 Late Collision
When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates
transmission. All remaining buffers for that frame are flushed and closed, and the LC bit is set in
the EIR register. The FEC will then continue to the next transmit buffer descriptor and begin
transmitting the next frame.
The “LC” interrupt will be asserted if enabled in the EIMR register.
MCF5271 Reference Manual, Rev. 2
Freescale Semiconductor
19-47