MCF5271CVM150J Freescale Semiconductor, MCF5271CVM150J Datasheet - Page 460

• Manufacturer Part Number: MCF5271CVM150J
• Description: IC MCU 166MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5271CVM150J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

UART Modules
After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a
non-zero character is received without a stop bit (framing error) and UnRXD remains low for
one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit
were detected. Parity error, framing error, overrun error, and received break conditions set the
respective PE, FE, OE, RB error and break flags in the USRn at the received character boundary
and are valid only if USRn[RxRDY] is set.
If a break condition is detected (UnRXD is low for the entire character including the stop bit), a
character of all zeros is loaded into the receiver holding register and USRn[RB,RxRDY] are set.
UnRXD must return to a high condition for at least one-half bit time before a search for the next
start bit begins.
The receiver detects the beginning of a break in the middle of a character if the break persists
through the next character time. If the break begins in the middle of a character, the receiver places
the damaged character in the Rx FIFO and sets the corresponding USRn error bits and
USRn[RxRDY]. Then, if the break lasts until the next character time, the receiver places an
all-zero character into the Rx FIFO and sets USRn[RB,RxRDY].
Figure 24-20
24-22
USRn[RxRDY]
USRn[FFULL]
USRn[OE]
1
Receiver
Enabled
UnRTS
Overrun
UMR2n[TxRTS] = 1
UnTXD
internal
module
select
shows receiver functional timing.
1
UOP0[RTS] = 1
Manually asserted first time,
automatically negated if overrun occurs
C1
Status
(C1)
Data
C2
Figure 24-20. Receiver Timing
MCF5271 Reference Manual, Rev. 2
C3
C4
C5 will
be lost
C5
Status
Data
(C2)
C6
C6, C7, and C8 will be lost
Automatically asserted
when ready to receive
Status
(C3)
Data
Freescale Semiconductor
Status
Data
(C4)
C7
command
Reset by
C8