MCF5271CVM150J Freescale Semiconductor, MCF5271CVM150J Datasheet - Page 481

• Manufacturer Part Number: MCF5271CVM150J
• Description: IC MCU 166MHZ 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF527xr

Specifications of MCF5271CVM150J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 97
• Program Memory Type: ROMless
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 196-MAPBGA
• Processor Series: MCF527x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5272-KIT, NNDK-MOD5270-KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

its low period. Therefore, synchronized clock I2C_SCL is held low by the device with the longest
low period.
Devices with shorter low periods enter a high wait state during this time (see
all devices concerned have counted off their low period, the synchronized clock I2C_SCL line is
released and pulled high. There is then no difference between the device clocks and the state of the
I2C_SCL line and all the devices start counting their high periods. The first device to complete its
high period pulls the I2C_SCL line low again.
The relative priority of the contending masters is determined by a data arbitration procedure. A
bus master loses arbitration if it transmits logic "1" while another master transmits logic "0". The
losing masters immediately switch over to slave receive mode and stop driving I2C_SDA output
(see
condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration.
Freescale Semiconductor
Figure
I2C_
I2C_
I2C_
I2C_SDA by
Master1
I2C_SDA by
Master2
25-7). In this case the transition from master to slave mode does not generate a STOP
SCL1
SCL2
I2C_SDA
I2C_SCL
SCL
Figure 25-8. Clock Synchronization
Figure 25-7. Arbitration Procedure
Internal Counter Reset
MCF5271 Reference Manual, Rev. 2
Wait
Master 2 Loses Arbitration,
and becomes slave-receiver
Start counting high period
Figure
I
2
C System Configuration
25-8). When
25-7