MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 148
![IC MCU 16BIT 25MHZ 132-PQFP](/photos/39/60/396098/4243113_sml.jpg)
MC68HC16Z1CEH25
Manufacturer Part Number
MC68HC16Z1CEH25
Description
IC MCU 16BIT 25MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
HC16r
Datasheet
1.MC68HC16Z1VEH16.pdf
(500 pages)
Specifications of MC68HC16Z1CEH25
Core Processor
CPU16
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Package
132PQFP
Family Name
HC16
Maximum Speed
25 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Number Of Programmable I/os
16
On-chip Adc
8-chx10-bit
Number Of Timers
11
Controller Family/series
68HC16
No. Of I/o's
16
Ram Memory Size
1KB
Cpu Speed
25MHz
No. Of Timers
2
Embedded Interface Type
QSPI, SCI
Rohs Compliant
Yes
Processor Series
HC16Z
Core
CPU16
Data Ram Size
1 KB
Interface Type
SCI, SPI, UART
Maximum Clock Frequency
25 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC16Z1CEH25
Manufacturer:
Freescale Semiconductor
Quantity:
135
Company:
Part Number:
MC68HC16Z1CEH25
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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5.6.4.2 LPSTOP Broadcast Cycle
5-42
BREAKPOINT OPERATION FLOW
Low-power stop mode is initiated by the CPU16. Individual modules can be stopped
by setting the STOP bits in each module configuration register. The SIM can turn off
system clocks after execution of the LPSTOP instruction. When the CPU16 executes
LPSTOP, the LPSTOP broadcast cycle is generated. The SIM brings the MCU out of
low-power mode when either an interrupt of higher priority than the interrupt mask lev-
el in the CPU16 condition code register or a reset occurs. Refer to
Operation
During an LPSTOP broadcast cycle, the CPU16 performs a CPU space write to ad-
dress $3FFFE. This write puts a copy of the interrupt mask value in the clock control
logic. The mask is encoded on the data bus as shown in
The LPSTOP CPU space cycle is shown externally (if the bus is available) as an indi-
cation to external devices that the MCU is going into low-power stop mode. The SIM
provides an internally generated DSACK response to this cycle. The timing of this bus
cycle is the same as for a fast termination write cycle. If the bus is not available (arbi-
trated away), the LPSTOP broadcast cycle is not shown externally.
1) SET R/W TO READ
2) SET FUNCTION CODE TO CPU SPACE
3) PLACE CPU SPACE TYPE 0 ON ADDR[19:16]
4) PLACE ALL ONES ON ADDR[4:2]
5) SET ADDR1 TO ONE
6) SET SIZE TO WORD
7) ASSERT AS AND DS
INITIATE HARDWARE BREAKPOINT PROCESSING
ACKNOWLEDGE BREAKPOINT
NEGATE DSACK or BERR
BERR during the LPSTOP broadcast cycle is ignored.
and
NEGATE AS or DS
CPU16
SECTION 4 CENTRAL PROCESSOR UNIT
Figure 5-15 Breakpoint Operation Flowchart
Freescale Semiconductor, Inc.
For More Information On This Product,
SYSTEM INTEGRATION MODULE
Go to: www.freescale.com
NOTE
ASSERT DSACK OR BERR TO INITIATE EXCEPTION PROCESSING
Figure
PERIPHERAL
for more information.
5-16.
CPU16 BREAKPOINT OPERATION FLOW
5.3.4 Low-Power
M68HC16 Z SERIES
USER’S MANUAL
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