MC68HC16Z1CEH25 Freescale Semiconductor, MC68HC16Z1CEH25 Datasheet - Page 431

• Manufacturer Part Number: MC68HC16Z1CEH25
• Description: IC MCU 16BIT 25MHZ 132-PQFP
• Manufacturer: Freescale Semiconductor
• Series: HC16r

Specifications of MC68HC16Z1CEH25

• Core Processor: CPU16
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 132-QFP
• Package: 132PQFP
• Family Name: HC16
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 16
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 11
• Controller Family/series: 68HC16
• No. Of I/o's: 16
• Ram Memory Size: 1KB
• Cpu Speed: 25MHz
• No. Of Timers: 2
• Embedded Interface Type: QSPI, SCI
• Rohs Compliant: Yes
• Processor Series: HC16Z
• Core: CPU16
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details

MPAR — MCCI Pin Assignment Register
ILSPI[2:0] — Interrupt Level for SPI
Bits [10:8] — Not Implemented
D.7.6 MCCI Pin Assignment Register
Bits [15:8], [7:4], 2 — Not Implemented
M68HC16 Z SERIES
USER’S MANUAL
15
0
RESET:
ILSPI[2:0] determine the interrupt request levels of SPI interrupts. Program this field
to a value from $0 (interrupts disabled) through $7 (highest priority). If the interrupt-
request level programmed in this field matches the interrupt-request level pro-
grammed for one of the SCI interfaces and both request an interrupt simultaneously,
the SPI is given priority.
The MPAR determines which of the SPI pins, with the exception of the SCK pin, are
actually used by the SPI submodule, and which pins are available for general-purpose
I/O. The state of SCK is determined by the SPI enable bit in SPCR1. Clearing a bit in
MPAR assigns the corresponding pin to general-purpose I/O; setting a bit assigns the
pin to the SPI. Refer to
SPI pins designated by the MPAR as general-purpose I/O are controlled only by
MDDR and PORTMC. The SPI has no effect on these pins. The MPAR does not affect
the operation of the SCI submodule.
14
0
13
0
12
0
NOTES:
1. MPA[7:4], MPA2 are not implemented.
MPAR Field
Freescale Semiconductor, Inc.
11
0
Table D-39 MPAR Pin Assignments
For More Information On This Product,
MPA0
MPA1
MPA3
—
—
—
—
—
Table
1
1
1
1
1
10
0
NOT USED
Go to: www.freescale.com
D-39.
REGISTER SUMMARY
9
0
MPAR Bit
8
0
—
—
—
—
—
0
1
0
1
0
1
7
6
Pin Function
5
PMC0
PMC1
PMC2
PMC3
PMC4
RXDB
PMC5
PMC6
RXDA
PMC7
MISO
MOSI
TXDB
TXDA
SCK
SS
4
MPA3
3
0
USED
NOT
2
$YFFC08
MPA1
1
0
MPA0
D-57
0
0