HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 12

IC SUPERH MPU ROMLESS 112QFP

HD6417034AFI20

Manufacturer Part Number
HD6417034AFI20
Description
IC SUPERH MPU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Rev. 7. 00 Jan 31, 2006 page x of xxvi
Item
2.4.1 Instruction
Set by Classification
Table 2.13
Arithmetic
Instructions
2.4.2 Operation
Code Map
Table 2.18
Operation Code
Map
8.5.3 Wait State
Control
10.4.5 Reset-
Synchronized PWM
Mode
Figure 10.31
Procedure for
Selecting Reset-
Synchronized PWM
Mode
10.4.6
Complementary
PWM Mode
Figure 10.33
Procedure for
Selecting
Complementary
PWM Mode
Page
37
42, 43
151
273
276
Revision (See Manual for Details)
Table amended
Table amended
Description amended
Regardless of the state of the WAIT signal, when the RW1 bit, the
number of wait states selected by CBR refresh wait state insertion
bits 1 and 0 (RLW1, RLW0) in the refresh control register (RCR)
are inserted into the CAS-before-RAS refresh cycle.
Description of PFC setting added
Description of PFC setting added
0110 Rn
Instruction Code
MSB
0000
0000
Instruction
MAC.W
MULS
MULU
0000
Rn
@Rm+,@Rn+
Rm,Rn
Rm,Rn
Fx
Fx
Rm
1001
1001
10MD SWAP.B
LSB MD: 00
Instruction Code
0100nnnnmmmm1111
0010nnnnmmmm1111
0010nnnnmmmm1110
Fx: 0000
NOP
Rm,Rn
Fx: 0001
MD: 01
DIV0U
SWAP.W
Rm,Rn
Operation
Signed operation of
(Rn)
MAC
16
Signed operation of
Rn
16
Unsigned operation of
Rn
16
16 + 42
16
16
Rm
Rm
(Rm) + MAC
32-bit
32-bit
MAC
MAC
Fx: 0010
MD: 10
MOVT Rn
NEGC
42-bit
Rm,Rn
Execution
Cycles
3/(2) *
1–3 *
1–3 *
Fx: 0011–1111
MD: 11
NEG
T Bit
Rm,Rn

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