HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 17

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

5.3
5.4
5.5
5.6
Section 6 User Break Controller (UBC)
6.1
6.2
6.3
6.4
6.5
Section 7 Clock Pulse Generator (CPG)
7.1
7.2
7.3
Section 8 Bus State Controller (BSC)
8.1
5.2.4
5.2.5
Register Descriptions ........................................................................................................ 74
5.3.1
5.3.2
Interrupt Operation............................................................................................................ 76
5.4.1
5.4.2
Interrupt Response Time ................................................................................................... 80
Usage Notes ...................................................................................................................... 81
Overview........................................................................................................................... 83
6.1.1
6.1.2
6.1.3
Register Descriptions ........................................................................................................ 86
6.2.1
6.2.2
6.2.3
Operation........................................................................................................................... 90
6.3.1
6.3.2
6.3.3
Setting User Break Conditions.......................................................................................... 93
Notes ................................................................................................................................. 94
6.5.1
6.5.2
6.5.3
Overview........................................................................................................................... 97
Clock Source ..................................................................................................................... 97
7.2.1
7.2.2
Usage Notes ...................................................................................................................... 100
Overview........................................................................................................................... 103
On-Chip Interrupts ............................................................................................... 71
Interrupt Exception Vectors and Priority Rankings ............................................. 71
Interrupt Priority Registers A–E (IPRA–IPRE) ................................................... 74
Interrupt Control Register (ICR) .......................................................................... 75
Interrupt Sequence ............................................................................................... 76
Stack after Interrupt Exception Handling............................................................. 79
Features ................................................................................................................ 83
Block Diagram ..................................................................................................... 84
Register Configuration......................................................................................... 85
Break Address Registers (BAR) .......................................................................... 86
Break Address Mask Register (BAMR)............................................................... 87
Break Bus Cycle Register (BBR)......................................................................... 88
Flow of User Break Operation ............................................................................. 90
Break on Instruction Fetch Cycles to On-Chip Memory...................................... 92
Program Counter (PC) Value Saved in User Break Interrupt Exception
On-Chip Memory Instruction Fetch..................................................................... 94
Instruction Fetch at Branches............................................................................... 94
Instruction Fetch Break........................................................................................95
Connecting a Crystal Resonator........................................................................... 97
External Clock Input ............................................................................................ 99
Processing ............................................................................................................ 92
........................................................................... 103
....................................................................... 83
....................................................................... 97
Rev. 7.00 Jan 31, 2006 page xv of xxvi