HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 199

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Note: * For details see section 8.11.3, Maximum Number of States from BREQ Input to Bus Release.
3.
8.10.2
1. BACK operation
2. Preventing spikes in the BACK signal
BREQ
BACK
BACK
BREQ
When an internal refresh is requested during an attempt to assert the BACK signal and BACK
is not asserted but remains high, a momentary narrow pulse-shaped spike may be output, as
shown below.
The following measures should be taken to prevent spikes in the BACK signal:
a. When BREQ is input to release the bus, make sure that a conflict with a refresh operation
b. A spike in the BACK signal has a narrow pulse width of approximately 2 to 5 ns, which
If a refresh request is generated during DMA transfer in burst mode, the DMA transfer is
halted and a refresh is executed.
does not occur. Stop the refresh operation or operate the refresh timer counter (RTCNT) or
the refresh time constant register (RTCOR) of the bus controller (BSC) to shift the refresh
timing.
can be eliminated by using a capacitor as shown in the figure below.
BACK
BACK Operation
BACK
BACK
Figure 8.37 BACK
Refresh request
If BACK has not gone low after waiting for the maximum
number of states* before the SuperH releases the bus, return
BREQ to the high level.
Refresh demand
BACK Operation in Response to Refresh Request (2)
BACK
BACK
BACK does not go low.
Spike pulse width is approx. 2 to 5 ns.
Rev. 7.00 Jan 31, 2006 page 171 of 658
Section 8 Bus State Controller (BSC)
REJ09B0272-0700