HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 370

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Watchdog Timer (WDT)
12.2.2
The timer control/status register (TCSR) is an eight-bit read/write register. TCSR differs from
other registers in being more difficult to write. See section 12.2.4, Register Access, for details. Its
functions include selecting the timer mode and clock source. Bits 7–5 are initialized to 000 by a
reset and in standby mode. Bits 2–0 are initialized to 000 by a reset, but retain their values in
standby mode.
Note: * Only 0 can be written, to clear the flag.
Bit 7—Overflow Flag (OVF): OVF indicates that TCNT has overflowed from H'FF to H'00 in
interval timer mode. It is not set in watchdog timer mode.
Bit 7: OVF
0
1
Bit 6—Timer Mode Select (WT/IT IT IT IT): WT/IT selects whether to use the WDT as a watchdog timer
or interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt
(ITI) or generates a WDTOVF signal, depending on the mode selected.
Bit 6: WT/IT IT IT IT
0
1
Rev. 7.00 Jan 31, 2006 page 342 of 658
REJ09B0272-0700
Bit
Initial value
Read/Write
Timer Control/Status Register (TCSR)
Description
No overflow of TCNT in interval timer mode
Cleared by reading OVF, then writing 0 in OVF
TCNT overflow in interval timer mode
Description
Interval timer mode: interval timer interrupt to the CPU when TCNT overflows
Watchdog timer mode: WDTOVF signal output externally when TCNT
overflows. Section 12.2.3, Reset Control/Status Register (RSTCSR), describes
in detail what happens when TCNT overflows in watchdog timer mode.
R/(W)*
OVF
7
0
WT/IT
R/W
6
0
TME
R/W
5
0
—
—
4
1
—
—
3
1
CKS2
R/W
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0