HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 7

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Organization of This Manual
Table 1 describes how this manual is organized. Figure 1 shows the relationships between the
sections within this manual.
Table 1
Category
Overview
CPU
Operating
Modes
Internal
Modules
Clock
Buses
Timers
Manual Organization
Section Title
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
Overview
CPU
Operating Modes —
Exception
Handling
Interrupt
Controller
User Break
Controller
Clock Pulse
Generator
Bus State
Controller
Direct Memory
Access
Controller
16-Bit Integrated
Timer Pulse Unit
Programmable
Timing Pattern
Controller
Watchdog Timer
Abbrevi-
ation
—
INTC
UBC
CPG
BSC
DMAC
ITU
TPC
WDT
—
CPU
Contents
layout, pin functions
instruction features, instruction types,
instruction lists
MCU mode, PROM mode
Resets, address errors, interrupts, trap
instructions, illegal instructions
interrupts, on-chip module interrupts
Break address and break bus cycle
selection
circuit
interface, refresh, wait state control, parity
control
peripheral module request, cycle steal
mode, burst mode
function, counter clear function, buffer
operation, PWM mode, complementary
PWM mode, reset synchronized mode,
synchronized operation, phase counting
mode, compare match output mode
Compare match output triggers, non-
overlap operation
Watchdog timer mode, interval timer mode
Features, internal block diagram, pin
Register configuration, data structure.
NMI interrupts, user break interrupts, IRQ
Crystal pulse generator, duty correction
Division of memory space, DRAM
Auto request, external request, on-chip
Waveform output mode, input capture
Rev. 7.00 Jan 31, 2006 page v of xxvi