HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 279

IC SUPERH MPU ROMLESS 112QFP

HD6417034AFI20

Manufacturer Part Number
HD6417034AFI20
Description
IC SUPERH MPU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Part Number:
HD6417034AFI20
Manufacturer:
Renesas Electronics America
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Manufacturer:
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Bit 0—Input Capture/Compare Match A (IMFA): IMFA indicates a GRA compare match or
input capture.
Bit 0: IMFA
0
1
10.2.12 Timer Interrupt Enable Register (TIER)
The timer status interrupt enable register (TIER) is an eight-bit read/write register that controls
enabling/disabling of overflow interrupt requests and general register compare match/input capture
interrupt requests. TIER is initialized to H'F8 or H'78 by a reset and in standby mode. Each ITU
channel has one TIER.
Table 10.10 Timer Interrupt Enable Register (TIER)
Channel
0
1
2
3
4
Note: * Undefined
Bits 7–3—Reserved: Bit 7 is read as undefined. Bits 6–3 are always read as 1. The write value to
bit 7 should be 0 or 1. The write value to bits 6–3 should always be 1.
Bit
Initial value
Read/Write
Abbreviation
TIER0
TIER1
TIER2
TIER3
TIER4
Description
Clearing condition:
Read IMFA when IMFA = 1, then write 0 in IMFA
DMAC is activated by an IMIA interrupt (only channels 0–3)
Setting conditions:
GRA is functioning as an output compare register and TCNT = GRA
GRA is functioning as an input capture register and the value of TCNT is
transferred to GRA by an input capture signal
7
*
Function
TIER controls interrupt enabling/disabling
6
1
5
1
Section 10 16-Bit Integrated Timer Pulse Unit (ITU)
4
1
Rev. 7.00 Jan 31, 2006 page 251 of 658
3
1
OVIE
R/W
2
0
REJ09B0272-0700
IMIEB
R/W
1
0
(Initial value)
IMIEA
R/W
0
0

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