HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 135

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

8.1.5
The SH microprocessors have a 32-bit address space in the architecture, but the upper 4 bits are
ignored. Table 8.3 outlines the space divisions. As shown, the space is divided into areas 0–7
according to the value of the upper addresses.
Each area is allocated a specific type of space. When the area is accessed, a strobe signal that
matches the type of area space is generated. This allocates peripheral chips and memory devices
according to the type of the area spaces and allows them to be directly linked to this chip. Some
areas are of a fixed type based on their address while others can be selected in registers.
Area 0 can be used as an on-chip ROM space or external memory space in the SH7034. In the
SH7032, it can only be used as external memory space. Area 1 can be used as DRAM space or
external memory space. DRAM space enables direct connection to DRAM and outputs RAS, CAS
and multiplexed addresses. Areas 2–4 can only be used as external memory space. Area 5 can be
used as on-chip supporting module space or external memory space. Area 6 can be used as
address/data multiplexed I/O space or external memory space. For address/data multiplexed I/O
space, an address and data are multiplexed and input/output from pins AD15–AD0. Area 7 can be
used as on-chip RAM space or external memory space.
The bus width of the data bus is basically switched between 8 bits and 16 bits according to the
value of address bit A27. For the following areas, however, the bus width is determined by
conditions other than the A27 bit value.
See table 8.6 in section 8.3, Address Space Subdivision, for more information on how the space is
divided.
On-chip ROM space in area 0: Always 32 bits
External memory space in area 0: 8 bits when MD0 pin is 0, 16 bits when the pin is 1
On-chip supporting module space in area 5: 8 bits when the A8 address bit is 0, 16 bits when it
is 1
Area 6: If A27 = 0, area 6 is 8 bits when the A14 address bit is 0, 16 bits when A14 is 1
On-chip RAM space in area 7: Always 32 bits
Overview of Areas
Rev. 7.00 Jan 31, 2006 page 107 of 658
Section 8 Bus State Controller (BSC)
REJ09B0272-0700