HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 122

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 User Break Controller (UBC)
6.5
6.5.1
Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on
the second of these two instructions but the contents of the UBC break condition registers are
changed so as to alter the break condition immediately after the first of the two instructions is
fetched, a user break interrupt will still occur when the second instruction is fetched.
6.5.2
When a conditional branch instruction or TRAPA instruction causes a branch, instructions are
fetched and executed as follows:
1. Conditional branch instruction, branch taken: BT, BF
2. TRAPA instruction, branch taken: TRAPA
When a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination will be fetched after the next instruction or the one after that does an overrun fetch.
When the next instruction or the one after that is set as a break condition, a branch will result in
the generation of a user break interrupt at the next instruction or the instruction after that, neither
of which instructions will be executed.
Rev. 7.00 Jan 31, 2006 page 94 of 658
REJ09B0272-0700
Instruction fetch cycles: Conditional branch fetch
but-one-instruction overrun fetch
Instruction execution: Conditional branch instruction execution
instruction execution
Instruction fetch cycles: TRAPA instruction fetch
but-one-instruction overrun fetch
Instruction execution: TRAPA instruction execution
execution
Notes
On-Chip Memory Instruction Fetch
Instruction Fetch at Branches
Branch destination fetch
Branch destination fetch
Next-instruction overrun fetch
Next-instruction overrun fetch
Branch destination instruction
Branch destination
Next-
Next-