HD64F2638F20J Renesas Electronics America, HD64F2638F20J Datasheet - Page 148

IC H8S MCU FLASH 256K 128-QFP

HD64F2638F20J

Manufacturer Part Number
HD64F2638F20J
Description
IC H8S MCU FLASH 256K 128-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheets

Specifications of HD64F2638F20J

Core Processor
H8S/2600
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SmartCard
Peripherals
Motor Control PWM, POR, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F2638F20J
Manufacturer:
PENESAS
Quantity:
252
Section 2 Instruction Descriptions
MAC (Multiply and ACcumulate)
Operand Format and Number of States Required for Execution
Notes
1. Flags (N, Z, V) indicating the result of the MAC instruction can be set in the condition-code
2. If ERn and ERm are the same register, the execution addresses are ERn and ERn + 2. After
3. If MACS is modified during execution of a MAC instruction, the result cannot be guaranteed.
Further Explanation of Instructions Using Multiplier
1. Modification of flags
Rev. 4.00 Feb 24, 2006 page 132 of 322
REJ09B0139-0400
Register
indirect with
post-increment
Addressing
register (CCR) by the STMAC instruction.
execution, the value of ERn is ERn + 4.
It is essential to wait for at least three states after a MAC instruction before modifying MACS.
The multiplier has N-MULT, Z-MULT, and V-MULT flags that indicate the results of MAC
instructions. These flags are separated from the condition-code register (CCR). The values of
these flags can be set in the N, Z, and V flags of the CCR only by the STMAC instruction.
N-MULT and Z-MULT are modified only by MAC instructions. V-MULT retains a value
indicating whether an overflow has occurred in the past, until it is cleared by execution of the
CLRMAC or LDMAC instruction.
The setting and clearing conditions for these flags are given below.
Mode
N-MULT (negative flag)
Saturating mode
Non-saturating mode
Mnemonic
MAC
@ERn+,
@ERm+
Operands
Set when bit 31 of register MACL is set to 1 by execution of a
MAC instruction
Cleared when bit 31 of register MACL is cleared to 0 by execution
of a MAC instruction
Set when bit 41 of register MACH is set to 1 by execution of a
MAC instruction
Cleared when bit 41 of register MACH is cleared to 0 by execution
of a MAC instruction
0
1st byte
1
6
2nd byte
Instruction Format
0
6
3rd byte
Multiply and Accumulate
D
0
ern
4th byte
0 erm
States
No. of
4